RV-Across: an associative processing simulator

Registro completo de metadados
MetadadosDescriçãoIdioma
Autor(es): dc.creatorSilveira, Jonathas Evangelista da-
Autor(es): dc.creatorFelzmann, Isaías Bittencout-
Autor(es): dc.creatorFabrício Filho, João-
Autor(es): dc.creatorWanner, Lucas Francisco-
Data de aceite: dc.date.accessioned2025-08-29T12:19:47Z-
Data de disponibilização: dc.date.available2025-08-29T12:19:47Z-
Data de envio: dc.date.issued2022-09-27-
Data de envio: dc.date.issued2022-09-27-
Data de envio: dc.date.issued2020-10-20-
Fonte completa do material: dc.identifierhttp://repositorio.utfpr.edu.br/jspui/handle/1/29753-
Fonte completa do material: dc.identifierhttps://doi.org/10.5753/wscad.2020.14064-
Fonte: dc.identifier.urihttp://educapes.capes.gov.br/handle/capes/1093312-
Descrição: dc.descriptionAssociative Processing provides high-performance and energyefficient parallel computation using a Content-Addressable Memory (CAM). Emerging big data applications can be significantly sped-up by Associative Processing, but validation and evaluation are key challenges. We present RVAcross, a RISC-V Associative Processing Simulator for testing, validation, and modeling associative operations. RV-Across eases the design of associative and near-memory processing architectures by offering interfaces to both building new operations and providing high-level experimentation. Our simulator records memory and registers states of each associative operation pass, giving the user visibility and control over the simulation. The user can employ the simulation statistics provided by RV-Across to compute performance and energy metrics. RV-Across implements common associative operations and provides a framework to allow for easy extension. We show how the simulator works by experimenting with different scenarios for associative operations with three applications that test the functionality of logic and arithmetic computations: matrix multiply, checksum, and bitcount. Our results highlight the direct relation between the data length and potential performance improvement of associative processing in comparison to regular CPU serial and parallel operation. In case of matrix multiplication, the speed-up increases linearly with matrices dimension, achieving 8X for 200x200 bytes matrices and overcoming parallel execution in an 8-core CPU.-
Formato: dc.formatapplication/pdf-
Idioma: dc.languageen-
Publicador: dc.publisherCampo Mourao-
Publicador: dc.publisherBrasil-
Relação: dc.relationSimpósio em Sistemas Computacionais de Alto Desempenho-
Relação: dc.relationhttps://sol.sbc.org.br/index.php/wscad/article/view/14064/13912-
Direitos: dc.rightsopenAccess-
Direitos: dc.rightshttp://creativecommons.org/licenses/by-nc/4.0/-
Palavras-chave: dc.subjectSimulação (Computadores)-
Palavras-chave: dc.subjectSistemas de memória de computadores-
Palavras-chave: dc.subjectInterfaces de usuário (Sistemas de computação)-
Palavras-chave: dc.subjectComputer simulation-
Palavras-chave: dc.subjectComputer storage devices-
Palavras-chave: dc.subjectUser interfaces (Computer systems)-
Palavras-chave: dc.subjectCNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO-
Título: dc.titleRV-Across: an associative processing simulator-
Tipo de arquivo: dc.typeaula digital-
Aparece nas coleções:Repositorio Institucional da UTFPR - RIUT

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