Enhancing performance of Gabriel graph-based classifiers by a hardware co-processor for embedded system applications.

Registro completo de metadados
MetadadosDescriçãoIdioma
Autor(es): dc.creatorArias Garcia, Janier-
Autor(es): dc.creatorMafra, Augusto Amaral-
Autor(es): dc.creatorGade, Liliane dos Reis-
Autor(es): dc.creatorCoelho, Frederico Gualberto Ferreira-
Autor(es): dc.creatorCastro, Cristiano Leite de-
Autor(es): dc.creatorTorres, Luiz Carlos Bambirra-
Autor(es): dc.creatorBraga, Antônio de Pádua-
Data de aceite: dc.date.accessioned2025-08-21T15:22:24Z-
Data de disponibilização: dc.date.available2025-08-21T15:22:24Z-
Data de envio: dc.date.issued2022-09-15-
Data de envio: dc.date.issued2022-09-15-
Data de envio: dc.date.issued2019-
Fonte completa do material: dc.identifierhttp://www.repositorio.ufop.br/jspui/handle/123456789/15312-
Fonte completa do material: dc.identifierhttps://ieeexplore.ieee.org/document/9072429-
Fonte completa do material: dc.identifierhttps://doi.org/10.1109/TII.2020.2987329-
Fonte: dc.identifier.urihttp://educapes.capes.gov.br/handle/capes/1012285-
Descrição: dc.descriptionIt is well known that there is an increasing interest in edge computing to reduce the distance between cloud and end devices, especially for Machine Learning (ML) methods. However, when related to latency-sensitive applications, little work can be found in ML literature on suitable embedded systems implementations. This paper presents new ways to implement the decision rule of a large margin classifier based on Gabriel graphs as well as an efficient implementation of this on an embedded system. The proposed approach uses the nearest neighbor method as the decision rule, and the implementation starts from an RTL pipeline architecture developed for binary large margin classifiers and proposes the integration in a hardware/software co-design. Results showed that the proposed approach was statistically similar to the classifier and had a speedup factor of up to 8x compared to the classifier executed in software, with performance suitable for ML latency-sensitive applications.-
Formato: dc.formatapplication/pdf-
Idioma: dc.languageen-
Direitos: dc.rightsrestrito-
Palavras-chave: dc.subjectMachine learning-
Palavras-chave: dc.subjectSystem on a chip-
Palavras-chave: dc.subjectLarge margin-
Palavras-chave: dc.subjectLatency sensitive-
Palavras-chave: dc.subjectIoT-
Título: dc.titleEnhancing performance of Gabriel graph-based classifiers by a hardware co-processor for embedded system applications.-
Aparece nas coleções:Repositório Institucional - UFOP

Não existem arquivos associados a este item.