Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications

Registro completo de metadados
MetadadosDescriçãoIdioma
Autor(es): dc.contributorUniversidade Estadual Paulista (UNESP)-
Autor(es): dc.contributorUniversidade de São Paulo (USP)-
Autor(es): dc.contributorimec-
Autor(es): dc.creatorSilva, V. C.P.-
Autor(es): dc.creatorMartino, J. A.-
Autor(es): dc.creatorSimoen, E.-
Autor(es): dc.creatorVeloso, A.-
Autor(es): dc.creatorAgopian, P. G.D.-
Data de aceite: dc.date.accessioned2025-08-21T21:38:54Z-
Data de disponibilização: dc.date.available2025-08-21T21:38:54Z-
Data de envio: dc.date.issued2025-04-29-
Data de envio: dc.date.issued2023-10-01-
Fonte completa do material: dc.identifierhttp://dx.doi.org/10.1016/j.sse.2023.108729-
Fonte completa do material: dc.identifierhttps://hdl.handle.net/11449/307667-
Fonte: dc.identifier.urihttp://educapes.capes.gov.br/handle/11449/307667-
Descrição: dc.descriptionThis work presents an experimental evaluation of n-type, gate-all-around (GAA), vertically stacked nanosheet field effect transistors (NSFETs) operating in a temperature (T) range from 473 K down to 173 K and focusing on their use for analog applications. Devices with gate lengths (Lgate) of 28 nm to 200 nm were analyzed. Besides exhibiting a slight short channel effect, the shorter transistors show a good performance in terms of analog application, presenting at 173 K an intrinsic voltage gain (AV) of 30 dB and unit gain frequency (fT) of 185 GHz. This is also seen in two figures of merit that characterize the transistor performance for analog circuit design: the transistor efficiency (gm/IDS) and the gain frequency product (AV*fT). The optimum region of operation was demonstrated to be at strong inversion by the trade-off between gm/IDS and fT, where in this region Lgate = 28 nm presents a gain frequency product of ∼ 5,5THz at T = 173 K. At lower temperature, as expected, it is confirmed that the carrier mobility and the subthreshold swing (SS) improve while the threshold voltage (VT) increases.-
Descrição: dc.descriptionUNESP Sao Paulo State University-
Descrição: dc.descriptionLSI/PSI/USP University of Sao Paulo-
Descrição: dc.descriptionimec-
Descrição: dc.descriptionUNESP Sao Paulo State University-
Idioma: dc.languageen-
Relação: dc.relationSolid-State Electronics-
???dc.source???: dc.sourceScopus-
Palavras-chave: dc.subjectAnalog operation-
Palavras-chave: dc.subjectHigh-temperature-
Palavras-chave: dc.subjectLow-temperature-
Palavras-chave: dc.subjectMOSFET-
Palavras-chave: dc.subjectNanosheets (NS)-
Título: dc.titleEvaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications-
Tipo de arquivo: dc.typelivro digital-
Aparece nas coleções:Repositório Institucional - Unesp

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