Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis

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Autor(es): dc.contributorUniversidade de São Paulo (USP)-
Autor(es): dc.contributorUniversidade Estadual Paulista (UNESP)-
Autor(es): dc.creatorde Lima Silva, Wenita-
Autor(es): dc.creatordo Nascimento Tolêdo, Rodrigo-
Autor(es): dc.creatorGonçalez Filho, Walter-
Autor(es): dc.creatorde Moraes Nogueira, Alexandro-
Autor(es): dc.creatorGhedini Der Agopian, Paula-
Autor(es): dc.creatorAntonio Martino, Joao-
Data de aceite: dc.date.accessioned2025-08-21T15:41:59Z-
Data de disponibilização: dc.date.available2025-08-21T15:41:59Z-
Data de envio: dc.date.issued2023-07-29-
Data de envio: dc.date.issued2023-07-29-
Data de envio: dc.date.issued2023-04-01-
Fonte completa do material: dc.identifierhttp://dx.doi.org/10.1016/j.sse.2023.108611-
Fonte completa do material: dc.identifierhttp://hdl.handle.net/11449/246870-
Fonte: dc.identifier.urihttp://educapes.capes.gov.br/handle/11449/246870-
Descrição: dc.descriptionThis work presents the comparison between Nanowire Tunnel Field-Effect Transistor (NW-TFET) and Line-TFET applied on the design of Low-Dropout Voltage Regulator (LDO). Both devices have a SiGe source composition in order to enhance the current drive. The transistors were modeled using lookup tables (LUTs) approach based on experimental data using Verilog-A language. The LDOs were designed for two conditions, considering different gm/ID, load currents and load capacitances. In order to compare the TFET LDOs with an established technology, a MOSFET LDO was designed with TSMC 0.18 µm process design kit. Both TFET LDOs reach stability without the presence of a compensation capacitor. For gm/ID = 10.5 V−1 the current consumption of NW-TFET LDO (1.5nA) is near two orders of magnitude lower than Line-TFET LDO (68nA) and three orders of magnitude lower than MOSFET LDO (9 µA). The Line-TFET LDO exhibits better results in almost all parameters despite of the gain-bandwidth product (GBW) that is in the same order of magnitude of the MOSFET LDO, 171 kHz compared to 250 kHz for gm/ID = 10.5 V−1. The comparison between TFET LDOs for gm/ID = 7 V−1 was also performed regarding the transient and process variability analysis. The transient response revealed that the Line-TFET LDO has a pronounced lower settling time, 71 µs compared to 5 ms for a load step, but with a damped oscillatory response, the NW-TFET LDO presented lower undershoot for the load step. The process variability analysis was performed for devices within the wafer and was observed that the Line-TFET LDO suffers a higher impact with a 20 dB variation on the loop gain in comparison to 10 dB in the NW-TFET LDO.-
Descrição: dc.descriptionLSI/PSI/USP University of Sao Paulo-
Descrição: dc.descriptionUNESP Sao Paulo State University-
Descrição: dc.descriptionUNESP Sao Paulo State University-
Idioma: dc.languageen-
Relação: dc.relationSolid-State Electronics-
???dc.source???: dc.sourceScopus-
Palavras-chave: dc.subjectAnalog circuit design-
Palavras-chave: dc.subjectLine-TFET-
Palavras-chave: dc.subjectLow-Dropout Voltage Regulator (LDO)-
Palavras-chave: dc.subjectNanowire-
Palavras-chave: dc.subjectProcess variability-
Palavras-chave: dc.subjectTunnel FET (TFET)-
Título: dc.titleComparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis-
Tipo de arquivo: dc.typelivro digital-
Aparece nas coleções:Repositório Institucional - Unesp

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