Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature

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MetadadosDescriçãoIdioma
Autor(es): dc.contributorUniversidade de São Paulo (USP)-
Autor(es): dc.contributorimec-
Autor(es): dc.contributorUniversidade Estadual Paulista (UNESP)-
Autor(es): dc.creatorSilva, Vanessa C.P.-
Autor(es): dc.creatorMartino, Joao A.-
Autor(es): dc.creatorSimoen, Eddy-
Autor(es): dc.creatorVeloso, Anabela-
Autor(es): dc.creatorAgopian, Paula G.D.-
Data de aceite: dc.date.accessioned2025-08-21T22:38:30Z-
Data de disponibilização: dc.date.available2025-08-21T22:38:30Z-
Data de envio: dc.date.issued2022-04-28-
Data de envio: dc.date.issued2022-04-28-
Data de envio: dc.date.issued2022-05-01-
Fonte completa do material: dc.identifierhttp://dx.doi.org/10.1016/j.sse.2022.108267-
Fonte completa do material: dc.identifierhttp://hdl.handle.net/11449/223545-
Fonte: dc.identifier.urihttp://educapes.capes.gov.br/handle/11449/223545-
Descrição: dc.descriptionIn this work the gate-all-around nanosheet transistor is analyzed at high temperatures, from analog point of view. At first, the gate-all-around nanosheet (NS) behavior is compared with reported omega-gate nanowire (NW) transistors, at room temperature. It is worth noting that the nanosheets devices present a stronger electrostatic coupling between gate and channel (lower short channel effect -SCE), and higher intrinsic voltage gain, AV (better Early voltage) when compared with NW devices (60 dB for NS and 55 db for NW, with L = 200 nm). Therefore, the second part of this work focuses on the analog study only for NS transistors (with different metal gate stacks), presenting the trade-off between transistor efficiency and unit gain frequency, fT from room temperature to 200 °C. The obtained results are very promising for both gate stack transistors, where values of transistor efficiency about 37 V−1 (T = 25 °C and L = 200 nm) and fT about 260 GHz (T = 25 °C and L = 28 nm) are obtained. The optimal application point was obtained at the transition from moderate to strong inversion.-
Descrição: dc.descriptionLSI/PSI/USP University of Sao Paulo-
Descrição: dc.descriptionimec-
Descrição: dc.descriptionUNESP Sao Paulo State University-
Descrição: dc.descriptionUNESP Sao Paulo State University-
Idioma: dc.languageen-
Relação: dc.relationSolid-State Electronics-
???dc.source???: dc.sourceScopus-
Palavras-chave: dc.subjectAnalog operation-
Palavras-chave: dc.subjectFT-
Palavras-chave: dc.subjectHigh temperature-
Palavras-chave: dc.subjectIntrinsic voltage gain-
Palavras-chave: dc.subjectMOSFET-
Palavras-chave: dc.subjectNanosheet (NS)-
Palavras-chave: dc.subjectNanowire (NW)-
Palavras-chave: dc.subjectTransistor efficiency-
Título: dc.titleTrade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature-
Tipo de arquivo: dc.typelivro digital-
Aparece nas coleções:Repositório Institucional - Unesp

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