Output conductance at saturation like region on Line-TFET for different dimensions

Registro completo de metadados
MetadadosDescriçãoIdioma
Autor(es): dc.contributorUniversidade de São Paulo (USP)-
Autor(es): dc.contributorUniversidade Estadual Paulista (Unesp)-
Autor(es): dc.creatorGoncalez Filho, Walter-
Autor(es): dc.creatorMartino, Joao A.-
Autor(es): dc.creatorAgopian, Paula G. D. [UNESP]-
Autor(es): dc.creatorIEEE-
Data de aceite: dc.date.accessioned2022-02-22T00:05:41Z-
Data de disponibilização: dc.date.available2022-02-22T00:05:41Z-
Data de envio: dc.date.issued2020-12-09-
Data de envio: dc.date.issued2020-12-09-
Data de envio: dc.date.issued2019-01-01-
Fonte completa do material: dc.identifierhttp://hdl.handle.net/11449/195388-
Fonte: dc.identifier.urihttp://educapes.capes.gov.br/handle/11449/195388-
Descrição: dc.descriptionThis work presents the behavior of Line Tunneling Field Effect Transistors (Line-TFET) at the saturation like region with different device's dimensions. In spite of the drain current and transconductance (gm) of the Line-TFET being proportional to the gate area (LgxW, with Lg: length and W:width), the output conductance (gd) is shown to be independent on the gate length at deep saturation. This unique behavior was observed experimentally and explained by numerical simulations. The conduction mechanisms are discussed and parasitic source to drain tunneling is found to be the main responsible for the output conductance value at the deep saturation like region, which doesn't depend upon Lg. Its impact on analog circuit design is also addressed, revealing fundamental differences of analog design using Line-TFET devices and MOSFET. It is revealed that if the designer wishes to increase the circuit voltage gain, this can be done by increasing the transconductance or the output resistance with Line-TFETs, as for MOSFETs only the latter option is available.-
Descrição: dc.descriptionCoordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)-
Descrição: dc.descriptionConselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)-
Descrição: dc.descriptionUniv Sao Paulo, LSI PSI USP, Sao Paulo, Brazil-
Descrição: dc.descriptionSao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, Brazil-
Descrição: dc.descriptionSao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, Brazil-
Formato: dc.format4-
Idioma: dc.languageen-
Publicador: dc.publisherIeee-
Relação: dc.relation2019 34th Symposium On Microelectronics Technology And Devices (sbmicro 2019)-
???dc.source???: dc.sourceWeb of Science-
Palavras-chave: dc.subjectLine TFET-
Palavras-chave: dc.subjectoutput conductance-
Palavras-chave: dc.subjectanalog circuit design-
Título: dc.titleOutput conductance at saturation like region on Line-TFET for different dimensions-
Aparece nas coleções:Repositório Institucional - Unesp

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